1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a ferroelectric random access memory cell having the ferroelectric capacitors.
2. Description of the Related Art
A ferroelectric random access memory (FeRAM) is a nonvolatile random access memory, utilizing ferroelectric capacitors as a memory device. Further, the FeRAM offers many advantages over other memories, in which the FeRAM is characterized by a relatively high operational speed, relatively low voltage programming, relatively low power consumption, and also radiation hardness. Because of these properties, the FeRAM is noted as a next-generation memory device.
The ferroelectric capacitor includes a bottom electrode, an upper electrode, and a high-k dielectric layer interposed between the bottom electrode and the upper electrode. The high-k dielectric layer has bistable polarization states. Thus, if a voltage is applied between the upper electrode and the bottom electrode, and an electric field above a coercive force (Ec) is generated, the high-k dielectric layer is polarized into one state. Then, even though an electric potential is lost, the high-k dielectric layer maintains the polarization state. If a voltage of an opposite direction to the above voltage is applied between the upper electrode and the bottom electrode, and an electric field above the coercive force (Ec) is generated with an opposite direction to the above electric field, the high-k dielectric layer is polarized into the other state. The FeRAM stores information using bistable polarization states of the high-k dielectric layer. Thus, in order to program and read information to the ferroelectric capacitor, it is necessary to apply a pulse-type voltage to the upper electrode.
Further, the ferroelectric capacitor has high capacitance. In the FeRAM, it is necessary to connect a limited number of ferroelectric capacitors to a common plate line, in order to apply a pulse-type voltage to the upper electrode, unlike DRAM. Therefore, the upper electrodes need to be separated from each other.
Further, in order to achieve a highly-integrated FeRAM, a higher number of capacitors should be formed inside a unit cell array, like DRAM. Therefore, the ferroelectric capacitors need to be formed three-dimensionally. A method of forming the ferroelectric capacitors three-dimensionally includes a trench-type capacitor and a box-type capacitor.
The method of forming the box-type capacitor is disclosed in U.S. Pat. No. 6,211,035 in the title of “Integrated circuit and method” to Moise, et al.
According to the disclosure by Moise, et al, a lower insulating layer is formed on a semiconductor substrate. Bottom electrodes are formed on the lower insulating layer. A high-k dielectric layer such as strontium bismuth tantalate (SrBi2Ta2O5; SBT) is conformally formed on the semiconductor substrate having the bottom electrodes, and then, an upper electrode layer is formed. Then, a diffusion barrier layer, a reflection preventive layer and photoresist are sequentially deposited. The photoresist is exposed and developed, thereby confining the positions of drive lines for a FeRAM cell array. Then, the reflection preventive layer, the diffusion barrier layer, the upper electrode layer, and the high-k dielectric layer are etched, using the patterned photoresist as a mask. Thus, box-type ferroelectric capacitors are formed.
In the method, it is advantageous that the box-type ferroelectric capacitors are formed, and a large number of these capacitors are formed inside a unit cell array. However, the method includes forming photoresist and patterning through photolithography in order to etch the upper electrode layer. Thus, the patterned photoresist should be aligned with the bottom electrodes. However, with a high-integration of the FeRAM, it is difficult to pattern the photoresist to be aligned with the bottom electrodes. Thus, a misalignment may be generated. The misalignment results in etch damage to an upper electrode.
Therefore, the method has a difficulty in fabricating highly-integrated ferroelectric capacitors while preventing the etch damage to the upper electrode.